ACS70310 datasheet(16/27 Pages) ALLEGRO

16 / 27 page

Very High Precision, Programmable Linear Hall-Effect Sensor IC

with Reverse Battery Protection and High-Bandwidth (240 kHz)

Analog Output for Core-Based Current Sensing

ACS70310

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The ACS70310 device uses a three-wire programming interface,

where VCC is used to control the program enable signal, data

is transmitted on VOUT, and all signals are referenced to GND.

This three-wire interface makes it possible to communicate with

multiple devices with shared VCC and GND lines.

The four transactions (Write Access, Write to EEPROM, Write

to Volatile Memory, and Read) are show in the figures on the

following pages. To initialize any communication, VCC should

be increased to a level above VprgH(min) without exceeding

VprgH(max). At this time, VOUT is disabled and acts as an input.

After program enable is asserted, the external controller must

drive the output low in a time less than td. This prevents the

device interpreting any false transients on VOUT as data pulses.

After the command is completed, VCC is reduced below VprgL,

back to normal operating level. Also, the output is enabled and

responds to magnetic input.

When performing a Write to EEPROM transaction, the

ACS70310 requires a delay of tw to store the data into the

EEPROM. The device will respond with a high-to-low transition

on VOUT to indicate the Write to EEPROM sequence is com-

plete.

When sending multiple command frames, it is not necessary to

toggle the program enable signal on VCC. After the first com-

mand frame is completed, and VCC remains at VprgH, the device

will ignore any subsequent pulses on the output. When the pro-

gram enable signal is brought below VprgL(max), the output will

respond to the magnetic input.

Synchronize

MSB

Memory Address

Data

CRC

Read/Write

0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

0/1

. . .

0/1 0/1

Figure 13: Command Frame General Format

Quantity of Bits

Name

Values

Description

Synchronization

Used to identify the beginning of a serial interface command

Read / Write

[As required] Write operation

[As required] Read operation

Address

0/1

[Read/Write] Register address (volatile memory or EEPROM)

Data

0/1

26 data bits and 6 ECC bits. For a read command frame the data consists of 32 bits: [31:28]

Don’t Care, [27:26] ECC Pass/Fail, and [25:0] Data. Where bit 0 is the LSB. For a write

command frame the data consists of 32 bits: [31:26] Don’t Care and [25:0] Data. Where bit 0 is

the LSB.

CRC

0/1

Bits to check the validity of frame.

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