GD25Q127CFJS datasheet(30/79 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q127C

driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,

the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1

during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is

protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed.

Figure20. 64KB Block Erase Sequence Diagram

7.19.

Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously

have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low,

followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.

The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The

command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been

latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase

cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check

the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and

is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block

Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors are

protected

Figure21. Chip Erase Sequence Diagram

7.20.

Deep Power-Down (DP) (B9H)

Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode

(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in

active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the

device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the

Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)

command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from

Deep Power-Down and Read Device ID (RDI) (ABH) or Enable Reset (66H) and Reset (99H) commands. These commands

can release the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command releases

Command

60H or C7H

CS#

SCLK

Command

D8H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

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