AM186ED-20KCSLASHW datasheet(21/88 Pages) AMD

21 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

PIN DESCRIPTIONS

Pins That Are Used by Emulators

The following pins are used by emulators: A19–A0,

AD7–AD0, ALE, BHE/ADEN, CLKOUTA, RD, S2–S0,

S6/CLKDIV2, and UZI.

Many emulators require S6/CLKDIV2 and UZI to be

configured in their normal functionality as S6 and UZI,

not as PIOs. If BHE/ADEN is held Low during the rising

edge of RES, S6 and UZI are configured in their normal

functionality.

Pin Terminology

The following terms are used to describe the pins:

Input—An input-only pin.

Output—An output-only pin.

Input/Output—A pin that can be either input or output

(I/O).

Synchronous—Synchronous inputs must meet setup

and hold times in relation to CLKOUTA. Synchronous

outputs are synchronous to CLKOUTA.

Asy n chr onous —In puts o r o u tp uts th at a r e

asynchronous to CLKOUTA.

A19–A0

(A19/PIO9, A18/PIO8, A17/PIO7)

Address Bus (output, three-state, synchronous)

These pins supply nonmultiplexed memory or I/O

addresses to the system one half of a CLKOUTA period

earlier than the multiplexed address and data bus

(AD15–AD0). During a bus hold or reset condition, the

address bus is in a high-impedance state.

While the Am186ED/EDLV microcontrollers are directly

connected to DRAM, A19–A0 will serve as the

nonmultiplexed address bus for SRAM, FLASH,

PROM, EPROM, and peripherals. The odd address

pins (A17, A15, A13, A11, A9, A7, A5, A3, and A1) will

have both the row and column address during a DRAM

space access. The odd address signals connect

directly to the row and column multiplexed address bus

of the DRAM. The even address pins (A18, A16, A14,

A12, A10, A8, A6, A4, A2, and A0) and A19 will have

the initial address asserted during the full DRAM

access. These signals will not transition during a

DRAM access.

AD15–AD8

Address and Data Bus (input/output, three-state,

synchronous, level-sensitive)

AD15–AD8—These time-multiplexed pins supply

memory or I/O addresses and data to the system. This

bus can supply an address to the system during the

first period of a bus cycle (t1). It supplies data to the

system during the remaining periods of that cycle (t2,

t3, and t4).

The address phase of these pins can be disabled. See

the ADEN description with the BHE/ADEN pin. When

WHB is deasserted, these pins are three-stated during

t2, t3, and t4.

During a bus hold or reset condition, the address and

data bus is in a high-impedance state.

During a power-on reset, the address and data bus

pins (AD15–AD0) can also be used to load system

configuration information into the internal reset

configuration register.

When accesses are made to 8-bit-wide memory

regions, AD15–AD8 drive their corresponding address

signals throughout the access. If the disable address

phase and 8-bit mode are selected (see the ADEN

description with the BHE/ADEN pin), then AD15–AD8

are three-stated during t1 and driven with their

corresponding address signal from t2 to t4.

AD7–AD0

Address and Data Bus (input/output, three-state,

synchronous, level-sensitive)

These time-multiplexed pins supply partial memory or

I/O addresses, as well as data, to the system. This bus

supplies the low-order 8 bits of an address to the

system during the first period of a bus cycle (t1), and it

supplies data to the system during the remaining

periods of that cycle (t2, t3, and t4). In 8-bit mode, AD7–

AD0 supplies the data for both high and low bytes.

The address phase of these pins can be disabled. See

the ADEN pin description with the BHE/ADEN pin.

When WLB is deasserted, these pins are three-stated

during t2, t3, and t4.

During a bus hold or reset condition, the address and

data bus is in a high-impedance state.

During a power-on reset, the address and data bus

pins (AD15–AD0) can also be used to load system

configuration information into the internal reset

configuration register.

ALE

Address Latch Enable (output, synchronous)

This pin indicates to the system that an address ap-

pears on the address and data bus (AD15–AD0). The

address is guaranteed to be valid on the trailing edge

of ALE. This pin is three-stated during ONCE mode.

ALE is three-stated and held resistively Low during a

bus hold condition. In addition, ALE has a weak internal

pulldown resistor that is active during reset, so that an

external device does not get a spurious ALE during

reset.

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