AM186ED-20KCSLASHW datasheet(28/88 Pages) AMD

28 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

they overlap. The PCS signals take precedence over

DRAM accesses when DRAM and memory-mapped

peripherals overlap.

PCS5 is three-stated and held resistively High during a

bus hold condition. In addition, PCS5 has a weak

internal pullup resistor that is active during reset.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asserts over a 256-

byte address range, which is twice the address range

covered by peripheral chip selects in the 80C186 and

80C188 microcontrollers. PCS5 also has extended

wait state options.

A1—When the EX bit in the MCS and PCS auxiliary

address bit 1 to the system. During a bus hold

condition, A1 retains its previously latched value.

PCS6/A2/PIO2

Peripheral Chip Select 6 (output, synchronous)

Latched Address Bit 2 (output, synchronous)

PCS6—This pin indicates to the system that a memory

access is in progress to the seventh region of the

peripheral memory block (either I/O or memory

address space). The base address of the peripheral

memory block is programmable.

The PCS chip selects can overlap either block of

DRAM. The PCS chip selects must have the same or

greater number of wait states as the bank of DRAM

they overlap. The PCS signals take precedence over

DRAM accesses when DRAM and memory-mapped

peripherals overlap.

PCS6 is three-stated and held resistively High during a

bus hold condition. In addition, PCS6 has a weak

internal pullup resistor that is active during reset.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asserts over a 256-

byte address range, which is twice the address range

covered by peripheral chip selects in the 80C186 and

80C188 microcontrollers. PCS6 also has extended

wait state options.

A2—When the EX bit in the MCS and PCS auxiliary

address bit 2 to the system. During a bus hold

condition, A2 retains its previously latched value.

PIO31–PIO0 (Shared)

Programmable I/O Pins (input/output,

asynchronous, open-drain)

The Am186ED/EDLV microcontrollers provide 32

individually programmable I/O pins. Each PIO can be

programmed with the following attributes: PIO function

(enabled/disabled), direction (input/output), and weak

pullup or pulldown. The pins that are multiplexed with

PIO31–PIO0 are listed in Table 2 and Table 3.

After power-on reset, the PIO pins default to various

configurations. The column titled

Power-On Reset

Status in Table 2 and Table 3 lists the defaults for the

PIOs. Most of the PIO pins are configured as PIO

inputs with pullup after power-on reset. The system

initialization code must reconfigure any PIO pins as

required.

The A19–A17 address pins default to normal operation

on power-on reset, allowing the processor to correctly

begin fetching instructions at the boot address

FFFF0h. The DT/R, DEN, and SRDY pins also default

to normal operation on power-on reset. PIO15 and

PIO24 should be set to normal operation before

enabling either bank of DRAM. PIO25 should be set to

normal operation before enabling the upper bank of

DRAM.

Read Strobe (output, synchronous, three-state)

RD—This pin indicates to the system that th e

microcontroller is performing a memory or I/O read

cycle. RD is guaranteed to not be asserted before the

address and data bus is floated during the address-to-

data transition. RD floats during a bus hold condition.

RES

Reset (input, asynchronous, level-sensitive)

This pin requires the microcontroller to perform a reset.

Wh en RE S i s ass e r t e d , th e mi cr oc on tr o l l e r

immediately terminates its present activity, clears its

internal logic, and transfers CPU control to the reset

address, FFFF0h.

RES must be held Low for at least 1 ms.

RES can be asserted asynchronously to CLKOUTA

because RES is synchronized internally. For proper

initialization, VCC must be within specifications, and

CLK O UTA mu st b e s t ab le fo r m o r e th an fo ur

CLKOUTA periods during which RES is asserted.

The microcontroller begins fetching instructions

approximately 6.5 CLKOUTA periods after RES is

deasserted. This input is provided with a Schmitt

trigger to facilitate power-on RES generation via an RC

network.

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