SSD1306Z datasheet(17/65 Pages) ETC2

17 / 65 page

SSD1306

Rev 1.1

P 17/59

Apr 2008

Solomon Systech

Table 8-3 : Control pins of 8080 interface

Function

RD#

WR#

CS#

D/C#

Write command

↑

Read status

↑

Write data

↑

Read data

↑

Note

(1) ↑ stands for rising edge of signal

(2) H stands for HIGH in signal

(3) L stands for LOW in signal

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline

processing is internally performed which requires the insertion of a dummy read before the first actual display

data read. This is shown in Figure 8-4.

Figure 8-4 : Display data read back procedure - insertion of dummy read

n+1

n+2

WR#

RD#

Databus

Write column

address

Read 1st data

Dummy read

Read 2nd data

Read 3rd data

8.1.3

MCU Serial Interface (4-wire SPI)

The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode,

D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to

D7, E and R/W# (WR#)# can be connected to an external ground.

Table 8-4 : Control pins of 4-wire Serial interface

Function

E(RD#)

R/W#(WR#)

CS#

D/C#

Write command Tie LOW

Tie LOW

↑

Write data

Tie LOW

↑

Note

(1) H stands for HIGH in signal

(2) L stands for LOW in signal

SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C#

is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data

RAM (GDDRAM) or command register in the same clock.

Under serial mode, only write operations are allowed.

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