SSD1306Z datasheet(32/65 Pages) ETC2

32 / 65 page

Solomon Systech

Apr 2008 P 32/59

Rev 1.1

SSD1306

5. Timing & Driving Scheme Setting Command Table

D/C#Hex

Command

Description

A[7:0]

Set Display Clock

Divide

Ratio/Oscillator

Frequency

A[3:0] : Define the divide ratio (D) of the

display clocks (DCLK):

Divide ratio= A[3:0] + 1, RESET is

0000b (divide ratio = 1)

A[7:4] : Set the Oscillator Frequency, FOSC.

Oscillator Frequency increases with

the value of A[7:4] and vice versa.

RESET is 1000b

Range:0000b~1111b

Frequency increases as setting value

increases.

A[7:0]

Set Pre-charge Period A[3:0] : Phase 1 period of up to 15 DCLK

clocks 0 is invalid entry

(RESET=2h)

A[7:4] : Phase 2 period of up to 15 DCLK

clocks 0 is invalid entry

(RESET=2h )

A[6:4]

Set VCOMH Deselect

Level

A[6:4] Hex

code

V COMH deselect level

000b

00h

~ 0.65 x VCC

010b

20h

~ 0.77 x VCC (RESET)

011b

30h

~ 0.83 x VCC

1 NOP

Command for no operation

Note

(1) “*” stands for “Don’t care”.

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