68HC705JB3 datasheet(9/134 Pages) FREESCALE

9 / 134 page

November 5, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05JB3

MOTOROLA

REV 1

vii

LIST OF FIGURES

Figure

Title

Page

1-1

MC68HC05JB3 Block Diagram........................................................................ 1-3

1-2

MC68HC05JB3 Pin Assignments .................................................................... 1-4

1-3

Oscillator Connections ..................................................................................... 1-5

2-1

MC68HC05JB3 Memory Map .......................................................................... 2-1

2-2

MC68HC05JB3 I/O Registers $0000-$000F.................................................... 2-3

2-3

MC68HC05JB3 I/O Registers $0010-$001F.................................................... 2-4

2-4

MC68HC05JB3 I/O Registers $0020-$002F.................................................... 2-5

2-5

MC68HC05JB3 I/O Registers $0030-$003F.................................................... 2-6

2-6

COP Register (COPR) ..................................................................................... 2-6

3-1

MC68HC05 Programming Model ..................................................................... 3-1

4-1

Interrupt Stacking Order................................................................................... 4-2

4-2

Interrupt Flowchart ........................................................................................... 4-3

4-3

External Interrupt (IRQ) Logic .......................................................................... 4-5

4-4

IRQ Control and Status Register (ICSR).......................................................... 4-5

5-1

Reset Sources.................................................................................................. 5-1

5-2

COP Watchdog Register (COPR) .................................................................... 5-3

6-1

STOP and WAIT Flowchart.............................................................................. 6-2

7-1

PB1 Slow Falling-edge Output ......................................................................... 7-5

8-1

Multi-Function Timer Block Diagram ................................................................ 8-1

8-2

Timer Counter Register.................................................................................... 8-3

8-3

Timer Control/Status Register (TCSR)............................................................. 8-3

9-1

Programmable Timer Block Diagram ............................................................... 9-1

9-2

Programmable Timer Counter Block Diagram ................................................. 9-2

9-3

Programmable Timer Counter Registers (TMRH, TMRL)................................ 9-3

9-4

Alternate Counter Block Diagram..................................................................... 9-4

9-5

Alternate Counter Registers (ACRH, ACRL).................................................... 9-4

9-6

Timer Input Capture Block Diagram................................................................. 9-5

9-7

TCAP Input Signal Conditioning....................................................................... 9-6

9-8

TCAP Input Comparator Output....................................................................... 9-7

9-9

Input Capture Registers (ICRH, ICRL)............................................................. 9-7

9-10

Timer Output Compare Block Diagram ............................................................ 9-9

9-11

Output Compare Registers (OCRH, OCRL) .................................................... 9-9

9-12

Timer Control Register (TCR) ........................................................................ 9-10

9-13

Timer Status Registers (TSR) ........................................................................ 9-11

10-1

USB Block Diagram ....................................................................................... 10-2

10-2

Supported Transaction Types per Endpoint................................................... 10-3

10-3

Supported USB Packet Types ....................................................................... 10-4

10-4

Sync Pattern................................................................................................... 10-4

10-5

SOP, Sync Signaling and Voltage Levels ...................................................... 10-5

10-6

CRC Block Diagram for Address and Endpoint Fields................................... 10-6

10-7

CRC Block Diagram for Data Packets ........................................................... 10-7

10-8

EOP Transaction Voltage Levels ................................................................... 10-8

10-9

EOP Width Timing.......................................................................................... 10-8

Freescale Semiconductor, Inc.

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