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IP4856CX25/C 데이터시트(PDF) 12 Page - Nexperia B.V. All rights reserved |
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IP4856CX25/C 데이터시트(HTML) 12 Page - Nexperia B.V. All rights reserved |
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12 / 22 page ![]() IP4856CX25_C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2 — 15 October 2014 11 of 21 NXP Semiconductors IP4856CX25/C SD 3.0-compliant memory card integrated dual voltage level translator 12. Dynamic characteristics 12.1 Voltage regulator Table 11. Voltage regulator Tamb =25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Voltage regulator output pin: VLDO tstartup(reg) regulator start-up time VCCA =1.8 V; VSUPPLY = 3.5 V; Cext =1 F; see Figure 5 - - 100 s tf(o) output fall time VO(reg) = 2.9 V to 1.8 V; SEL = LOW to HIGH; see Figure 4 -- 1 ms tr(o) output rise time VO(reg) = 1.8 V to 2.9 V; SEL = HIGH to LOW; see Figure 4 - - 100 s Fig 4. Regulator mode change timing Measuring points: ENABLE signal at 0.5 VCCA and regulator output signal at 0.97 VO(reg). Fig 5. Regulator start-up time 001aah981 VI GND 97 % 50 % tstartup(reg) VO(reg) regulator output ENABLE 0 V |
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