ST7SB20JSLASHUS datasheet(24/154 Pages) STMICROELECTRONICS

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ST7232A

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

6.3.3 External Power-On RESET

To start up the microcontroller correctly, the user

must ensure by means of an external reset circuit

that the reset signal is held low until VDD is over

the minimum level specified for the selected fOSC

frequency.

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

6.3.4 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 13.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

Figure 13. RESET Sequences

RESET PIN

EXTERNAL

WATCHDOG

th(RSTL)in

RUN

WATCHDOG UNDERFLOW

tw(RSTL)out

RUN

RESET

SOURCE

EXTERNAL

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

ACTIVE

PHASE

ACTIVE

PHASE

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