ST7SB20JSLASHUS datasheet(31/154 Pages) STMICROELECTRONICS

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ST7232A

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INTERRUPTS (Cont’d)

Table 8. Interrupt Mapping

Note 1: Unexpected exit from HALT may occur when SPI is in slave mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by

the IPA, IPB and ISxx bits of the EICR register

(Figure 18). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

Each external interrupt source can be generated

on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

■ Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity

bits in the EICR register can be modified only

when the I1 and I0 bits of the CC register are both

set to 1 (level 3). This means that interrupts must

be disabled before changing sensitivity.

The pending interrupts are cleared by writing a dif-

ferent value in the ISx[1:0], IPA or IPB bits of the

EICR.

N°

Source

Block

Description

Label

Priority

Order

Exit

from

HALT

Exit

from

ACTIVE

HALT

Address

Vector

RESET

Reset

N/A

yes

FFFEh-FFFFh

TRAP

Software interrupt

FFFCh-FFFDh

Not used

FFFAh-FFFBh

MCC/RTC

Main clock controller time base inter-

rupt

MCCSR

Higher

Priority

yes

FFF8h-FFF9h

ei0

External interrupt port A3..0

N/A

yes

FFF6h-FFF7h

ei1

External interrupt port F2..0

yes

FFF4h-FFF5h

ei2

External interrupt port B3..0

yes

FFF2h-FFF3h

ei3

External interrupt port B7..4

yes

FFF0h-FFF1h

Not used

FFEEh-FFEFh

SPI

SPI peripheral interrupts

SPICSR

yes 1)

FFECh-FFEDh

TIMER A

TIMER A peripheral interrupts

TASR

FFEAh-FFEBh

TIMER B

TIMER B peripheral interrupts

TBSR

FFE8h-FFE9h

SCI

SCI Peripheral interrupts

SCISR

Lower

Priority

FFE6h-FFE7h

Not used

FFE4h-FFE5h

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