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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SAFC161PI 데이터시트(PDF) 18 Page - Infineon Technologies AG |
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SAFC161PI 데이터시트(HTML) 18 Page - Infineon Technologies AG |
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18 / 400 page  &3, $UFKLWHFWXUDO2YHUYLHZ User’s Manual 2-2 1999-08 2.1 Basic CPU Concepts and Optimizations The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware is provided for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Figure 2-2 CPU Block Diagram To meet the demand for greater performance and flexibility, a number of areas has been optimized in the processor core. Functional blocks in the CPU core are controlled by signals from the instruction decode logic. These are summarized below, and described in detail in the following sections: 1) High Instruction Bandwidth / Fast Execution 2) High Function 8-bit and 16-bit Arithmetic and Logic Unit 3) Extended Bit Processing and Peripheral Control 4) High Performance Branch-, Call-, and Loop Processing 5) Consistent and Optimized Instruction Formats 6) Programmable Multiple Priority Interrupt Structure |
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