DLPC6421 datasheet(36/49 Pages) TI1

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DLPC6421

DLPS117A – JULY 2018 – REVISED APRIL 2019

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10 Layout

10.1 Layout Guidelines

TI recommends 2-ounce copper planes in the PCB design to achieve needed thermal connectivity.

10.1.1 PCB Layout Guidelines for Internal DLPC6421 Power

TI recommends the following guidelines to achieve desired DLPC6421 performance relative to internal PLLs:

•

The DLPC6421 device contains four PLLs (PLLM1, PLLM2, PLLD & PLLS), each of which have a dedicated

1.1-V digital supply, and three (PLLM1, PLLM2 & PLLD) which have a dedicated 1.8-V analog supply. It is

important to have filtering on the supply pins that covers a broad frequency range. Each 1.1-V PLL supply pin

should have individual high frequency filtering in the form of a ferrite bead and a 0.1 µF ceramic capacitor.

These components should be located very close to the individual PLL supply balls. The impedance of the

ferrite bead should be much greater than that of the capacitor at frequencies above 10 MHz. The 1.1-V to the

PLL supply pins should also have low frequency filtering in the form of an RC filter. This filter can be common

to all the PLLs. The voltage drop across the resistor is limited by the 1.1-V regulator tolerance and the

DLPC6421 device voltage tolerance. A resistance of 0.36 Ω and a 100 µF ceramic are recommended.

•

The analog 1.8-V PLL power pins should have a similar filter topology as the 1.1-V. In addition, TI

recommends that the 1.8-V be generated with a dedicated linear regulator.

•

When designing the overall supply filter network, care must be taken to ensure no resonance occurs.

Particular care must be taken around the 1- to 2-MHz band, as this coincides with the PLL natural loop

frequency.

DLPC6421 데이터시트(PDF) 36 Page - Texas Instruments