DS624A1

37

CS5368

5.5

03h (OVFM) Overflow Mask Register

Default:

0xFF, all overflow interrupts enabled.

The Overflow Mask Register is used to allow or prevent individual channel overflow events from

creating activity on the OVFL pin. When a particular bit is set low in the Mask register, the

corresponding overflow bit in the Overflow Status register is prevented from causing any activity

on the OVFL pin.

5.6

04h (HPF) High-Pass Filter Register

Default:

0x00, all high-pass filters enabled.

The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each

channel. These filters are used to perform DC offset calibration, a procedure that is detailed in

“DC Offset Control” on page 26

.

5.7

05h Reserved

5.8

06h (PDN) Power Down Register

Default:

0x00 - everything powered up

The Power Down Register is used as needed to reduce the chip’s power consumption.

Bit[7] RESERVED

Bit[6] RESERVED

Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.

Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscil-

lator core is shut down, and no clock is supplied to the chip. If the chip is running off an externally

supplied clock at the MCLK pin, it is also prevented from clocking the device internally.

Bit[3:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial

data outputs are forced to all zeroes.

R/W

7

654

3

21

0

R/W

OVFM8

OVFM7

OVFM6

OVFM5

OVFM4

OVFM3

OVFM2

OVFM1

R/W

7

654

3

21

0

R/W

HPF8

HPF7

HPF6

HPF5

HPF4

HPF3

HPF2

HPF1

R/W

7

654

3

21

0

Reserved

--

--

---

-

R/W

7

654

3

21

0

R/W

RESERVED

PDN-BG

PDN-OSC

PDN87

PDN65

PDN43

PDN21