CS5378 datasheet(59/86 Pages) CIRRUS

59 / 86 page

CS5378

DS639F1

ceived, the MFLAG bit is set in the next output

word. See “Modulator Interface” on page 36 for

more information about MFLAG.

Time Break Bit - TB

The time break bit marks a timing reference based

on a rising edge into the TIMEB pin. After a pro-

grammed delay, the TB bit in the status byte is set

for one output sample. The TIMEBRK digital fil-

ter register (0x29) programs the sample delay for

the TB bit output. See “Time Break Controller” on

page 63 for more information about time break.

FIFO Overflow Bit - W

The FIFO overflow bit indicates an error condition

in the serial data FIFO, and is set if new digital fil-

ter data overwrites a FIFO location containing data

which has not yet been sent.

The W bit is sticky, meaning it persists indefinitely

once set. Clearing the W bit requires sending the

‘Filter Stop’ and ‘Filter Start’ configuration com-

mands to reinitialize the data FIFO.

Conversion Data Word

The lower 24-bits of the serial data word is the con-

version sample for the specified channel. Conver-

sion data is 24-bit two’s complement format.

16.3 Serial Data Transactions

The CS5378 automatically initiates serial data

transactions whenever data becomes available in

the output FIFO by driving the DRDY pin low.

Once a serial data transaction is initiated, serial

clocks received into SCK cause data to be output to

MISO, as shown in Figure 35. When all available

data is read from the serial data FIFO, DRDY is re-

leased.

DRDY

SCK

MISO

Figure 35. SD Port Transaction

MSB

LSB

CS5378 데이터시트(PDF) 59 Page - Cirrus Logic