CS42432-DMZ datasheet(45/62 Pages) CIRRUS

45 / 62 page

DS673PP2

The Digital-to-Analog converters of the CS42432 will mute the output following the reception of 8192

consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute.

Detection and muting is done independently for each channel. The quiescent voltage on the output

will be retained during the mute period. The muting function is affected, similar to volume control

changes, by the Soft and Zero Cross bits (SZC[1:0]).

7.7.4

MUTE ADC SERIAL PORT (MUTE ADC_SP)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, the ADC Serial Port will be muted.

7.8

DAC CHANNEL MUTE (ADDRESS 07H)

7.8.1

INDEPENDENT CHANNEL MUTE (AOUTX_MUTE)

Default = 0

0 - Disabled

1 - Enabled

Function:

The respective Digital-to-Analog converter outputs of the CS42432 will mute when enabled. The qui-

escent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and

Zero Cross bits (DAC_SZC[1:0]).

7.9

AOUTX VOLUME CONTROL (ADDRESSES 08H-0D)

7.9.1

VOLUME CONTROL (AOUTX_VOL[7:0])

Default = 00h

Function:

The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB incre-

ments from 0 dB to -127.5 dB. Volume settings are decoded as shown in Table 6. The volume chang-

es are implemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0]). All volume settings

less than -127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel.

654

Reserved

AOUT6_MUTE

AOUT5_MUTE

AOUT4_MUTE

AOUT3_MUTE

AOUT2_MUTE

AOUT1_MUTE

654

AOUTx_VOL7

AOUTx_VOL6

AOUTx_VOL5

AOUTx_VOL4

AOUTx_VOL3

AOUTx_VOL2

AOUTx_VOL1

AOUTx_VOL0

CS42432-DMZ 데이터시트(PDF) 45 Page - Cirrus Logic

CS42432-DMZ 데이터시트(HTML) 45 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

데이터시트 다운로드

링크 URL