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CS61310 데이터시트(PDF) 13 Page - Cirrus Logic

부품명 CS61310
상세설명  T1 INE INTERFACE UNIT
PDF  30 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS61310 데이터시트(HTML) 13 Page - Cirrus Logic

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CS61310
DS440F1 FEB ‘03
13
An address/command byte, shown in Figure 10,
points to addresses 0x10 through 0x15 (address
0x10 shown), and precedes a data byte. The first
bit of the address/command byte determines
whether a read or a write is requested. The next six
bits contain the address. The last bit is ignored.
Data to the internal registers is input on the eight
clock
cycles
immediately
following
the
ad-
dress/command byte.
CS
SC L K
SD O
CL K E = 0
SD I
D6
D5
D4
D3
D2
D1
D0
D7
0
0
D7
D6
D5
D4
D3
D2
D1
D0
A ddre ss/C o m m a nd Byte
D a ta Input/O utp u t
0
0
0
1
0
R/W
Figure 10. Input/Output Timing (showing address 0x10)
7
6
5
4
3
210
ADDR
Control Register 1
(CR1)
TAOS
LLOOP
RLOOP
LB02
LB01
CODER
TAZ
NLOOP
LOS
0x10 R/W
Control Register 2
(CR2)
AIS
RAMPLSE
RSVD
set to “0”
LOOPDN
LOOPUP
RPWDN
TxHIZ
RSVD
set to “0”
0x11 R/W
Equalizer Gain
(EQGAIN)
X
X
X
EQ4
EQ3
EQ2
EQ1
EQ0
0x12 R
RAM Address
(RAM)
MSB
-
-
---
-
LSB
0x13 R/W
Reserved
Set to “0”
0
0
0
0
0
000
0x14
Table 3. Register Map



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