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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM29BDS643D 데이터시트(PDF) 1 Page - Advanced Micro Devices |
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AM29BDS643D 데이터시트(HTML) 1 Page - Advanced Micro Devices |
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1 / 46 page  PRELIMINARY This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 23709 Rev: A Amendment/+3 Issue Date: December 21, 2000 Refer to AMD’s Website (www.amd.com) for the latest information. Am29BDS643D 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory DISTINCTIVE CHARACTERISTICS s Single 1.8 volt read, program and erase (1.7 to 1.9 volt) s Multiplexed Data and Address for reduced I/O count — A0–A15 multiplexed as D0–D15 — Addresses are latched with AVD# control inputs while CE# low s Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations s Read access times at 54 MHz/40 MHz — Burst access times of 13.5/20 ns @ 30 pF at industrial temperature range — Asynchronous random access times of 90/90 ns @ 30 pF — Synchronous random access times of 106/120 ns @ 30 pF s Burst length — Continuous linear burst s Power dissipation (typical values, 8 bits switching, CL = 30 pF) — Burst Mode Read: 25 mA — Simultaneous Operation: 40 mA — Program/Erase: 15 mA — Standby mode: 0.2 µA s Sector Architecture — Eight 4 Kword sectors and one hundred twenty-seven 32 Kword sectors — Bank A contains the eight 4 Kword sectors and thirty-one 32 Kword sectors — Bank B contains ninety-six 32 Kword sectors s Sector Protection — Software command sector locking — WP# protects the last two boot sectors — All sectors locked when VPP = VIL s Handshaking feature — Provides host system with minimum possible latency by monitoring RDY s Software command set compatible with JEDEC 42.4 standards — Backwards compatible with Am29F and Am29LV families s Minimum 1 million erase cycle guarantee per sector s 20-year data retention at 125 °C — Reliable operation for the life of the system s Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses s Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion s Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset input (RESET#) — Hardware method to reset the device for reading array data s CMOS compatible inputs, CMOS compatible outputs s Low VCC write inhibit s 48-Ball FBGA package |
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