전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ST92195D 데이터시트(PDF) 63 Page - STMicroelectronics

부품명 ST92195D
상세설명  48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER
PDF  249 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST92195D 데이터시트(HTML) 63 Page - STMicroelectronics

Back Button ST92195D Datasheet HTML 59Page - STMicroelectronics ST92195D Datasheet HTML 60Page - STMicroelectronics ST92195D Datasheet HTML 61Page - STMicroelectronics ST92195D Datasheet HTML 62Page - STMicroelectronics ST92195D Datasheet HTML 63Page - STMicroelectronics ST92195D Datasheet HTML 64Page - STMicroelectronics ST92195D Datasheet HTML 65Page - STMicroelectronics ST92195D Datasheet HTML 66Page - STMicroelectronics ST92195D Datasheet HTML 67Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 63 / 249 page
background image
63/249
ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU)
4.5 RESET CONTROL UNIT REGISTERS
The RCCU consists of two registers. They are
PCONF and SDRATH. Unless otherwise stated,
unused register bits must be kept in their reset val-
ue in order to avoid problems with the device be-
haviour.
PLL CONFIGURATION REGISTER (PCONF)
R251 - Read/Write
Register Page: 55
Reset value: 0000 0111 (07h)
Bit 7= SRESEN.
Software Reset Enable.
0: RCCU PLL and CSDU are turned off when a
HALT instruction is performed.
1: RCCU will reset the microcontroller when a
HALT instruction is performed.
Bits 6:0= Reserved bits. Leave in their reset state.
CLOCK SLOW DOWN UNIT RATIO REGISTER
(SDRATH)
R254 - Read/Write
Register Page: 55
Reset value:
0010 0xxx (2xh) after software reset
0100 0xxx (4xh) after watchdog reset
0000 0000 (00h) after external reset
Bit 7 = Reserved bit. Leave in its reset state.
Bit 6 = WDGRES.
Watchdog Reset. WDGRES is
automatically set if the last reset was a watchdog
Reset. This is a read only bit.
Bit 5 = SFTRES.
Software Reset. SFTRES is au-
tomatically set if the last reset was a software Re-
set. This is a read only bit.
Bits 4:0 = Reserved bits. Please leave in their re-
set state.
70
SRESEN
0
0
0
0
1
1
1
70
0
WDGRE
S
SFTRE
S
00
x
x
x



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com