ST92195D datasheet(65/249 Pages) STMICROELECTRONICS

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ST92195C/D - TIMING AND CLOCK CONTROLLER

FREQUENCY MULTIPLIERS (Cont’d)

For the Off-chip filter components please refer to

the Required External Components figure provid-

ed in the first section of the data sheet.

The frequency multipliers are off during and upon

exiting from the reset phase. The user must pro-

gram the desired multiplying factor, start the multi-

plier and then wait for its stability (refer to the Elec-

trical Charateristics chapter for the specified de-

lay).

Once the Core/Peripherals multiplier is stabilized,

the Main Clock controller can be re-programmed

(through the FMSL bit, MCCR.6) to provide the fi-

nal frequency (INTCLK) to the CPU.

The

frequency

multipliers

are

automatically

switched off when the µP enters in HALT mode

(the HALT mode forces the control register to its

reset status).

Table 12. Examples of CPU speed choice

Note: 24 MHz is the max. CPU authorized frequency.

Table 13. DOTCK/2 frequency choices

(*) Preferred values for 4/3.

(**) 16/9 screen formats.

Note: 18 MHz is the min. DOTCK/2 authorized frequency.

Table 14. Data Slicer over-sampling clock

(other values are not allowed)

Table 15. External PLL Filter Stabilisation time

Crystal

Frequency

FML

(3:0)

Internal Frequency

(Fimf)

4 MHz

10 MHz

4 MHz

12 MHz

4 MHz

14 MHz

4 MHz

16 MHz

4 MHz

18 MHz

4 MHz

24 MHz

SKW

(3:0)

DOTCK/2

18 MHz

20 MHz(*)

22 MHz

24 MHz (**)

Crystal

Frequ.

Prescale

factor

Multiply

factor

7x Text

Frequency (Fslic)

4 MHz

777

48.5625 MHz

8 MHz

128

777

48.5625 MHz

Clock Pin Name

Clock Name

Control Register

Stabilization Period

MCFM

Main Clock PLL Filter Input Pin

MCCR

35 ms.

PXFM

Pixel Clock PLL Filter Input Pin

PXCCR

35 ms

TXCF

Teletext PLL Clock Filter input Pin

SLCCR

200 ms

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