ST92195D datasheet(64/249 Pages) STMICROELECTRONICS

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ST92195C/D - TIMING AND CLOCK CONTROLLER

5 TIMING AND CLOCK CONTROLLER

5.1 FREQUENCY MULTIPLIERS

Three on-chip frequency multipliers generate the

proper frequencies for: the Core/Real time Periph-

erals, the Display related time base and the Slicer

over-sampling clock for the Teletext Data slicer.

For both the Core and the Display frequency mul-

tipliers, a 4 bit programmable feed-back counter

allows the adjustment of the multiplying factor to

the application need (a 4 MHz or 8 MHz crystal is

assumed).

Figure 32. Timing and Clock Controller Block Diagram

Frequency

Multiplier

FML(3:0)

FMEN

Xtal

Oscillator

Asynch.

Handler

FMSL

Main Clock Controller

Divide

by 2

TXCF

MCFM

OSCIN

OSCOUT

Fimf

Divide

by 2

to CSYNC Controller,

SYNC Extractor, ..

SLDIV2

FMEN

Frequency

Multiplier

SLIEN

( x 777 )

48.56 MHz Clock

Divide

by 64

(Teletext SLicer)

Frequency

Multiplier

Skew Corrector

Synchronized DOTCK / 2 to Display

SKWL(3:0)

SKWEN

Hsync

SKHPLS

PXFM

(Synchronized DOTCK)

Divide

by 2

(2X Pixel clock for 1X width characters)

4 MHz real time Clock

Divide

by 2

to Teletext Display Storage RAM (TRI)

Div-2

MODER.5

SKDIV2

VR02095A

Async.

Handler

Memory Wait

BREQ

WFI

CPUCLK

Prescaler

1 to 8

Clock

Control

INTCLK

ST9 Clock Control Unit (RCCU)

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