ST92195D datasheet(117/249 Pages) STMICROELECTRONICS

117 / 249 page

117/249

ST92195C/D - ON SCREEN DISPLAY (OSD)

ON SCREEN DISPLAY (Cont’d)

7.4.6.3 Building a Serial Mode, 40-Char, Line

Mode Display

Half-Page Location

The 0.5 Kbyte block of half-page content is stored

in the TDSRAM location pointed to by the

PG3..PG0 bits.

Header & Status Rows Location

The 0.5 Kbyte block containing the Header, Status

Row 0 and Status Row 1 is pointed to by the

HS3..HS0 bits. The Row attribute (row count) is

stored in this block at offset 100h and contains 12

bytes for line mode (see DCM1R register descrip-

tion).

Row Scrolling Buffer Location

The scrolling buffer corresponds to Row 12 when

the scrolling feature is used (in this case 11 rows

are scrolled).

Figure 73. Serial (40 Characters) Line Mode Mapping

0.5K TDSRAM

Row 1

Row 11

Row 12/ Scrolling Buffer

Free Space

Resolution 0.5K bytes

See Figure 70 on

page 115 for

Address Values

0.5K TDSRAM

Header Char.

Resolution 0.5K bytes

Status Row 0

Status Row 1

Free Space

Row Attr.

Free Space

100h

Block

Number

(0.5K)

TDSRAM

Address

(hex.)

TDPR

Value

(Hex.)

PG3..PG0

8000

8200

8400

8600

8800

8A00

8C00

8E00

9000

9200

9400

9600

9800

9A00

9C00

9E00

ST92195D 데이터시트(PDF) 117 Page - STMicroelectronics

ST92195D 데이터시트(HTML) 117 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL