ST92195D datasheet(143/249 Pages) STMICROELECTRONICS

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ST92195C/D - SYNC CONTROLLER

SYNC CONTROLLER (Cont’d)

7.5.4.3 Free-Running Monitor Sync Mode

This mode is accessed when the MOD1 bit is set.

In this mode, the chassis HSYNC and VSYNC sig-

nals are not used. They are replaced by the sync

signals which are fully Crystal based (use of the in-

ternal main 4 MHz Clock).

Two free-running monitor modes are available:

when the MOD0 bit is reset the Composite Sync

output (CSO) is generated for a 60Hz format;

when the MOD0 bit is set to “1” the Composite

Sync output (CSO) is generated for a 50Hz format.

For both formats, the TV line period is 64µs.

The Composite Sync alternate function Output

(CSO) can be activated or disabled under control

of the VSEP bit.

In Free-Running Monitor Sync mode, the VPOL

control bit is used to control whether an interlaced

or non-interlaced TV context must be generated.

When the non-interlaced context is programmed,

only the “1st TV Field” configuration is generated.

Figure 85. Even/Odd Field Timings

1st TV Field

2nd TV Field

623

624

625

311

312

313

314

315

316

317

318

319

622

523

524

525

522

(50 Hz Mode)

(60 Hz Mode)

310

261

262

263

264

265

266

267

268

269

260

(50 Hz Mode)

(60 Hz Mode)

d2 = 2.25 µs

d1 = 4.75 µs

VR02092C

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