ST92195D datasheet(159/249 Pages) STMICROELECTRONICS

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ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT

TELETEXT SLICER AND ACQUISITION UNIT (Cont’d)

ACQUISITION PACKET REQUEST REGISTER

(ACQPRR)

R251 - Read/Write

Reset value: 0xxx 0000 (00h)

Bit 7 = HAMF:

Hamming Check mode control.

This bit is set and cleared by software.

0: Hamming 8/4 correction

1: Hamming 24/18 correction

Bit 6 = Reserved bit.

Bit 5 = FR7B:

Framing Code 7 Matching Bits Error.

This bit is set by hardware when only 7 of the 8

framing code bits are valid. This bit must be reset

by software.

0: No error

1: 7-bits of 8-bit framing code matched

Bit 4 = FRDET:

Acknowledge Framing Code 7

Bits.

This bit is set and cleared by software.

0: Framing codes that match on only 7 bits are not

acknowledged.

1: Acknowledge Framing codes that match on only

7 bits

Bit 3 = SPF:

Service Packet Flag.

This bit is set by hardware and cleared by soft-

ware. The type of service packet requested is pro-

grammed using the P[29:31] bits.

0: No service packet received

1: Service packet is received and was requested.

Bits 2:0 = P[31:P29]:

X/29, X/30, X/31 Packet

Control.

These bits are programmed by software before

each VBI.

0: Service packets Px are never stored.

1: Service packets Px will be stored.

TELETEXT QUALITY MEASURE REGISTER

(ACQTQMR)

R252 - Read/Write

Reset value: 0000 0000 (00h)

Bits 7:4 = HEC[3:0]:

Hamming Errors Counter.

These bits contain the error counter value. When

an overflow occurs, the incrementation is stopped

at the value Fh. The counter is reset by Hardware

at each Vsync. HEC[3] is the most significant bit.

Bits 3:0 = BLC[3:0]:

Bad Line Counter.

These bits contain the error counter value. When

an overflow occurs, the incrementation is stopped

to the value Fh. The counter is reset by Hardware

at each Vsync. BLC[3] is the most significant bit.

HAMF

FR7B FRDET

SPF

P31

P30

P29

HEC3

HEC2

HEC1

HEC0

BLC3

BLC2

BLC1

BLC0

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