AX58200 datasheet(49/180 Pages) ASIX

49 / 180 page

AX58200

EtherCAT Slave Controller SoC

0x400D_1000

– 0x400D_1FFF

USCI1_BA

USCI1 Control Registers

System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)

0xE000_E010

– 0xE000_E0FF

SCS_BA

System Timer Control Registers

0xE000_E100

– 0xE000_ECFF

SCS_BA

External Interrupt Controller Control Registers

0xE000_ED00

– 0xE000_ED8F

SCS_BA

System Control Registers

Table 2.2-7: Address Space Assignments for On-Chip Controllers

2.2.7

SRAM Memory Organization

The AX58200 supports embedded SRAM with total 160 Kbytes size and the SRAM organization is separated to

three banks: SRAM bank0 and SRAM bank1 and SRAM bank2. The first bank has 32 Kbytes address space, the

second bank has 96 Kbyte address space and the third bank has 32Kbyte. These three banks address space can be

accessed simultaneously. The SRAM bank0 supports parity error check to make sure chip operating more stable.

The SRAM bank2 is shared with SPIM cache, it can switch to external SPI Flash cache memory. Note that SRAM

bank2 has additional two wait cycles when reading data.

⚫

Supports total 160 Kbytes SRAM

⚫

Supports byte / half word / word write

⚫

Supports fixed 32 Kbytes SRAM bank0 for independent access

⚫

Supports parity error check function for SRAM bank0

⚫

Supports oversize response error

⚫

Supports remap address to 0x1000_0000

AHB interface

controller

SRAM decoder

SRAM bank0

SRAM bank1

SRAM decoder

AHB interface

controller

AHB interface

controller

SRAM decoder

SRAM bank2

Figure 2.2-9: SRAM Block Diagram

Figure 2.2-9 shows the SRAM organization of AX58200. There are three SRAM banks in AX58200. The bank0

is addressed to 32 Kbytes, the bank1 is addressed to 96 Kbytes and the bank2 is addressed to 32 Kbyte. The bank0

address space is from 0x2000_0000 to 0x2000_7FFF. The bank1 address space is from 0x2000_8000 to

0x2001_FFFF. The bank2 address space is from 0x2002_0000 to 0x2002_7FFF. The address between

0x2002_8000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal

memory addresses.

The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can access SRAM bank0 through

0x2000_0000 to 0x2000_7FFF or 0x1000_0000 to 0x1000_7FFF, and access SRAM bank1 through 0x2000_8000

to 0x2001_FFFF or 0x1000_8000 to 0x1001_FFFF, and access SRAM bank2 through 0x2002_0000 to

0x2002_7FFF or 0x1002_0000 to 0x1002_7FFF.

AX58200 데이터시트(PDF) 49 Page - ASIX Electronics Corporation

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