TFP503

PanelBus HDCP DIGITAL RECEIVER

SLDS149 − AUGUST 2004

14

POST OFFICE BOX 655303

TFP503 clocking and data synchronization (continued)

The input clock to the TFP503 is conditioned by a PLL (phase-locked-loop) to remove high frequency jitter from

the clock. The PLL provides four 10x clock outputs of different phases to locate and sync the T.M.D.S. data

streams (4x oversampling). During the active display interval, the pixel data is encoded to be transition

minimized; whereas, during the blanking interval, the control data is encoded to be transition maximized. A

DVI-compliant transmitter is required to transmit during the blanking interval for a minimum period of time,

code. Performing synchronization during the blanking interval, when the data is transition maximized, assures

reliable data bit boundary detection. Phase synchronization to the data streams is unique for each of the three

input channels and is maintained as long as the link remains active.

TFP503 T.M.D.S. input levels and input impedance matching

The TFP503 is internally optimized using a laser-trim process to precisely fix the single-ended termination

impedance at 50

Ω. This fixed impedance eliminates the need for external termination resistors while providing

optimum impedance matching to standard DVI cables having a characteristic impedance of 100

Ω.

Figure 14 shows a conceptual schematic of a TFP510 or TFP513 transmitter and TFP503 receiver connection.

The TFP510 or TFP513 transmitter drives the twisted-pair cable via a current source, usually achieved with an

open-drain output driver. The internal single-ended termination resistors, which are matched to the

disconnected and the TFP503 DVI inputs are left unconnected, the TFP503 receiver inputs are pulled up to

designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common mode voltages

_

+

Internal

Termination at 50

Ω

AVCC

DVI-Compliant Cable

DATA

DATA

TI TFP503 Receiver

TI TFP510 or TFP513 Transmitter

Current

Source

Figure 14. T.M.D.S. Differential Input and Transmitter Connection

1/2 VID

AVCC

AVCC - 1/2 VID

+ 1/2 VID

- 1/2 VID

VID

a ) Single-Ended Input Signal

b) Differential Input Signal

Figure 15. T.M.D.S. Inputs