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AS8846 데이터시트(PDF) 4 Page - ams AG |
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AS8846 데이터시트(HTML) 4 Page - ams AG |
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4 / 35 page ![]() Data Sheet AS8446 Revision 1.8, Date 2005-03-17 Page 4 of 35 Pin Description The AS8446 Motor Driver/Controller contains the driver/controller chip in a SOIC28 package The complete PWM DC Motor Regulator board needs an additional µP to close the regulation loop and control the whole regulator (dual package solution, free choice of the controlling µP). Pinout AS8446 Figure 1 Pinout AS 8446 Pin Description AS8446, Pin Types S … power supply AI … analog in AO … analog out AIO … analog in/out DI … digital in DIPU … digital in with pull-up DIPD … digital in with pull-down DO … digital out DIO … digital in/out DO_T … digital out, tristate LV … low voltage HV … high voltage Pin Name Type Note 1 CMN HV AI Current Measurement Input (negative side) 2 CMP HV AI Current Measurement Input (positive side) 3 VMO HV AI Motor Voltage Input 4 Vbat S Battery Voltage, Main Supply 5 TP HV AI Temperature Sensor Input 6 FAIL LV DO Error Status Output of AS8446 7 CS LV DIPU Chip Select, Enable Pin of Three Wire Interface 8 ADC HV AO Analog Measurement Output (multiplexed) 9 Wake-up HV AIO Wake-up Pin 10 n.c. 11 Tst 1 LV DIPU Test Pin 1 (1) 12 Tst 2 LV DO Test Pin 2 (2) 13 DATAin LV DIPD Data Input of the Three-Wire Interface 14 DATAout LV DO_T Data Output of the Three- Wire Interface 15 Clk LV DIPD Clock of the Three-Wire Interface 16 PWM LV DIPU PWM Input (Control of the Power FET Driver) 17 Tst 3 LV DO Test Pin 3 (2) 18 WD LV DIPU Watch Dog Input 19 RESET LV DO Reset Output (controlled by Watch Dog) 20 Iref LV AIO Reference Current Pin 21 VDD AI VDD feedback input 22 VDDctrl HV AO VDD supply (5 V generated by the on chip voltage regulator) 23 CP1 HV AIO Charge Pump Capacitor (Vbat side) 24 CP2 HV AIO Charge Pump Capacitor (Vpump side) 25 Vpump AO Charge Pump Buffer Capacitor 26 OUT HV AO Power FET Driver Output 27 GND_P S Power Ground 28 VSS S Digital/Analog Ground Table 2 PIN description of AS 8446 Note (1) Must be connected to VDD Note (2) Must be left open TP Wake-Up Vbat VSS Iref VDDctrl VDD CP2 CP1 Vpump OUT GND_P CS CMP DATAout CMN FAIL PWM 25 26 24 23 22 21 20 19 18 17 16 Clk DATAin Tst 1 Tst 2 27 28 RESET 1 15 2 3 4 5 6 7 8 9 10 11 12 13 14 VMO ADC WD Tst 3 n.c. |
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