DP83261AVF datasheet(34/132 Pages) NSC

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60 Control Information (Continued)

Current Receiver Status Register (CRS0)

The Current Receiver Status Register (CRS0) records the status of the Receiver state machine It is continuously updated It

remains stable when accessed

When in Diagnose Mode this register is frozen on an internal error until the internal error event is cleared by resetting the

RSMERR bit in the Internal Event Latch Register

ACCESS RULES

Address

Read

Write

0Ch

Always

Data Ignored

RFLG

RS2

RS1

RS0

RES

RTS2

RTS1

RTS0

Bit

Symbol

Description

D0 – 2

RTS(0 – 2)

Receive Timing State

RTS(0 – 2) represent the current state of the Receiver Timing state

machine The encoding is shown below

RTS2

RTS1

RTS0

Receive Timing State

Await

Check

INFO

Check

MAC

Reserved

RES

Reserved

D4–6

RS(0–2)

Receive State

RS(0 – 2) represent the current state of the Receive state machine that

implements the ANSI standard MAC Receive Functions The encoding is shown below

RS2

RS1

RS0

Receive State

Listen

Await

CTRL (Receive FC)

BODY (Rec FR Body)

STATUS (A

C Ind)

CHECK

TOKEN (Check Token)

STATUS (Optional Ind)

Reserved

RFLG

Flag

Current value of the Restricted Flag When not holding the token indicates the type of

the last valid token received When holding the token indicates the type of token that will be

issued at the end of the current service opportunity

0 Non-restricted

1 Restricted

DP83261AVF 데이터시트(PDF) 34 Page - National Semiconductor (TI)

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