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ASL4501SHN 데이터시트(PDF) 9 Page - NXP Semiconductors |
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ASL4501SHN 데이터시트(HTML) 9 Page - NXP Semiconductors |
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9 / 43 page ![]() ASL4501SHN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2 — 10 January 2018 9 of 43 NXP Semiconductors ASL4501SHN Four-phase boost converter 8.2.1 Virtual phase configuration The ASL4501SHN can generate up to four internal phases at up to two virtual outputs. With the internal phase control enable registers, it can be selected, how many virtual phases are generated for the individual virtual outputs. Fig 5. Mapping of virtual phases (V1_1 to V2_4) to physical phases (G1 to G4) aaa-015305 V1_1 CONTROL LOOP 1 FLEXIBLE MAPPING VIA REGISTER SETTINGS CONTROL LOOP 2 V1_2 V1_3 G1 G2 G3 G4 V1_4 V2_1 V2_2 V2_3 V2_4 Table 4. Internal phase control enable for phase logic 1 (address 0Bh) Bit Symbol Description Value Function 7 to 4 - reserved 0000 reserved for future use: keep clear 3 EN_P4_1 phase 4 enabled 0 phase 4 is off 1 phase 4 is enabled 2 EN_P3_1 phase 3 enabled 0 phase 3 is off 1 phase 3 is enabled 1 EN_P2_1 phase 2 enabled 0 phase 2 is off 1 phase 2 is enabled 0 EN_P1_1 phase 1 enabled 0 phase 1 is off 1 phase 1 is enabled Table 5. Internal phase control enable for phase logic 2 (address 0Ch) Bit Symbol Description Value Function 7 to 4 - reserved 0000 reserved for future use: keep clear 3 EN_P4_2 phase 4 enabled 0 phase 4 is off 1 phase 4 is enabled 2 EN_P3_2 phase 3 enabled 0 phase 3 is off 1 phase 3 is enabled 1 EN_P2_2 phase 2 enabled 0 phase 2 is off 1 phase 2 is enabled 0 EN_P1_2 phase 1 enabled 0 phase 1 is off 1 phase 1 is enabled |
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