LPC5410X datasheet(26/95 Pages) NXP

26 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

26 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute

to a boolean expression. The boolean expression consists of specified levels

and/or transitions on various combinations of these pins.

– Each bit slice minterm (product term) comprising of the specified boolean

expression can generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can also be programmed to generate an RXEV

notification to the CPU. The RXEV signal can be connected to a pin.

– Pattern match can be used in conjunction with software to create complex state

machines based on pin inputs.

– Pattern match engine facilities wake-up only from active and sleep modes.

7.15 AHB peripherals

7.15.1 DMA controller

The DMA controller allows peripheral-to memory, memory-to-peripheral, and

memory-to-memory transactions. Each DMA stream provides unidirectional DMA

transfers for a single source and destination.

7.15.1.1 Features

• 22 channels, 21 of which are connected to peripheral DMA requests. These come

from the USART, SPI, and I2C peripherals. One spare channels has no DMA request

connected, and can be used for functions such as memory-to-memory moves.

• DMA operations can be triggered by on- or off-chip events. Each DMA channel can

select one trigger input from 20 sources. Trigger sources include ADC interrupts,

Timer interrupts, pin interrupts, and the SCT DMA request lines.

• Priority is user selectable for each channel.

• Continuous priority arbitration.

• Address cache.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.

7.16 Digital serial peripherals

7.16.1 USART

7.16.1.1 Features

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Maximum bit rates of 6.25 Mbit/s in asynchronous mode.

• Maximum supported bit rate of 24 Mbit/s for USART master and slave synchronous

modes.

• 7, 8, or 9 data bits and 1 or 2 stop bits.

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