LPC5410X datasheet(36/95 Pages) NXP

36 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

36 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

7.20.4.4 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the RTC power

domain and the RESET pin. The LPC5410x can wake up from deep power down mode

via the RESET pin and the RTC alarm.

7.20.5 Brownout detection

The LPC5410x includes a monitor for the voltage level on the VDD pin. If this voltage falls

below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In

addition, a separate threshold levels can be selected to cause chip reset and interrupt.

7.20.6 Safety

The LPC5410x includes a Windowed WatchDog Timer (WWDT), which can be enabled

by software after reset. Once enabled, the WWDT remains locked and cannot be modified

in any way until a reset occurs.

7.21 Code security (Code Read Protection - CRP)

This feature of the LPC5410x allows user to enable different levels of security in the

system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry can be invoked by pulling a pin on the LPC5410x LOW on reset.

This pin is called the ISP entry pin.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. CRP3 fully disables any access to the chip via SWD and ISP. It is up to the user’s

application to provide (if needed) flash update mechanism using IAP calls or a call to

reinvoke ISP command to enable a flash update via USART.

4. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code

can be disabled (No_ISP mode). For details, see the LPC5410x user manual.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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