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VSC7440 데이터시트(PDF) 355 Page - Microsemi Corporation |
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VSC7440 데이터시트(HTML) 355 Page - Microsemi Corporation |
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355 / 444 page ![]() VCore-III System and CPU Interfaces VMDS-10492 VSC7440 Datasheet Revision 4.2 338 Figure 118 • SIMC SPI Clock Configurations Data is sampled in the middle of the data-eye. When using SPI protocol and transferring more than one data frame at the time, the controller performs one consecutive transfer. The following illustration shows a transfer of three data frames of 4 bits each. Note: Transmitting transfers end when the transmit FIFO runs out of data frames. Receive only transfers end when the pre-defined number of data-frames is read from the SI interface. Figure 119 • SIMC SPI 3x Transfers 4.8.2.2 SSP Protocol The SSP protocol for transferring two 6-bit data frames is shown in the following illustration. When using SSP mode, CTRLR0.SCPH and CTRLR0.SCPOL must remain zero. SI_nCS0 SI_CLK SI_DO SI_DI 75 4 3 2 1 0 CTRLR0.SCPH = 0, CTRLR0.SCPOL = 0 6 SI_nCS0 SI_CLK SI_DO SI_DI 75 4 3 2 1 0 CTRLR0.SCPH = 1, CTRLR0.SCPOL = 0 6 SI_nCS0 SI_CLK SI_DO SI_DI 75 4 3 2 1 0 CTRLR0.SCPH = 1, CTRLR0.SCPOL = 1 6 SI_nCS0 SI_CLK SI_DO SI_DI 75 4 3 2 1 0 CTRLR0.SCPH = 0, CTRLR0.SCPOL = 1 6 75 4 3 2 1 0 6 75 4 3 2 1 0 6 75 4 3 2 1 0 6 75 4 3 2 1 0 6 SI_nCS0 SI_CLK SI_DO SI_DI 3 1 0 3 210 First frame 2 3 1 0 3 210 2 32 10 32 10 Second frame Third frame |
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