VSC7440 datasheet(359/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

342

MEMCTRL_CFG.DDR_WIDTH

Set to 0 when using 1 byte lane.

Set to 1 when using 2 byte lanes.

MEMCTRL_CFG.MSB_COL_ADDR

Set to one less than the number of column address bits

for the modules.

MEMCTRL_CFG.MSB_ROW_ADDR

Set to one less than the number of row address bits for

the modules. See field description for example.

MEMCTRL_CFG.BANK_CNT

Set to 1.

MEMCTRL_CFG.BURST_LEN

Set to 1.

MEMCTRL_CFG.BURST_SIZE

Set to same value as MEMCTRL_CFG.DDR_WIDTH.

MEMCTRL_CFG.DDR_ECC_ENA

Set to 0 during initialization of the memory controller.

MEMCTRL_CFG.DDR_ECC_COR_ENA

Set to 0 during initialization of the memory controller.

MEMCTRL_CFG.DDR_ECC_ERR_ENA

Set to 0 during initialization of the memory controller.

MEMCTRL_CFG.DDR_512MBYTE_PLUS

Set to 0 during initialization of the memory controller.

MEMCTRL_REF_PERIOD.REF_PERIOD

Set to (tREFI(ns)/3.2ns) round down to the nearest

integer.

MEMCTRL_REF_PERIOD.MAX_PEND_REF

Set to 8.

MEMCTRL_TIMING0.RD_DATA_XFR_DLY

Set to (RL-3).

MEMCTRL_TIMING0.WR_DATA_XFR_DLY

Set to (WL-1).

MEMCTRL_TIMING0.RD_TO_PRECH_DLY

Set to (BL-1).

MEMCTRL_TIMING0.WR_TO_PRECH_DLY

Set to (WL+BL+tWR-1).

MEMCTRL_TIMING0.RAS_TO_PRECH_DLY

Set to (tRAS(min)-1).

MEMCTRL_TIMING0.RD_CS_CHANGE_DLY

Set to BL.

MEMCTRL_TIMING0.WR_CS_CHANGE_DLY

Set to (BL-1).

MEMCTRL_TIMING0.RD_TO_WR_DLY

Set to (RL+BL+1-WL).

MEMCTRL_TIMING1.WR_TO_RD_DLY

Set to (WL+BL+tWTR-1).

MEMCTRL_TIMING1.RAS_TO_CAS_DLY

Set to (tRCD-1).

MEMCTRL_TIMING1.RAS_TO_RAS_DLY

Set to (tRRD-1).

MEMCTRL_TIMING1.PRECH_TO_RAS_DLY

Set to (tRP-1).

MEMCTRL_TIMING1.BANK8_FAW_DLY

Set to (FAW-1).

MEMCTRL_TIMING1.RAS_TO_RAS_SAME_BANK_DLY Set to (tRC-1).

MEMCTRL_TIMING2.INIT_DLY

Set to (ID-1) during initialization of the memory controller.

MEMCTRL_TIMING2.REF_DLY

Set to (tRFC-1).

MEMCTRL_TIMING2.MDSET_DLY

Set to (MD-1).

MEMCTRL_TIMING2.PRECH_ALL_DLY

Set to (RP-1).

MEMCTRL_TIMING3.WR_TO_RD_CS_CHANGE_DLY

Set to (WL+tWTR-1).

MEMCTRL_TIMING3.LOCAL_ODT_RD_DLY

Set to (RL-3).

MEMCTRL_TIMING3.ODT_WR_DLY

Set to (OW-1).

MEMCTRL_TIMING3.ODT_RD_DLY

Set to (OR-1).

MEMCTRL_MR0_VAL.MR0_VAL

Set to MR0.

Table 251 •

Memory Controller Configuration (continued)

Description

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