VSC7440 datasheet(385/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

368

information, see Interrupt Destination Configuration. An active and enabled interrupt source sets

INTR_IDENT.INTR_IDENT[n].

On rare occasions it is desirable to bypass the stickiness of interrupt sources and use

INTR_RAW.INTR_RAW[n] directly instead of INTR_STICKY.INTR_STICKY[n]. Set

INTR_BYPASS.INTR_BYPASS[n] to enable bypass and ignore INTR_STICKY and INTR_TRIGGER

configurations.

Note: The bypass function may be useful for some software interrupt handler architectures. It should only be

used for interrupt sources that are guaranteed to be sticky in the source block. For example, the GPIO

interrupts that are generated from sticky bits in DEVCPU_GCB::GPIO_INTR may be applicable for the

bypass mode.

4.8.13.2 Interrupt Destination Configuration

The four interrupt destinations are handled identically in the interrupt controller. This section describes

destination d, which refers to the replication index of that interrupt in the DST_INTR_* registers. The

following illustration shows the logic associated with a single interrupt destination.

Figure 131 •

Interrupt Destination Logic

The interrupt destination can enable individual sources for interrupt by writing a mask to

DST_INTR_MAP[d].DST_INTR_MAP. When a source is enabled in DST_INTR_MAP then an interrupt

from this source will be propagated to the interrupt destination.

The currently active and enabled source interrupts for a destination can be seen by reading

DST_INTR_IDENT[d].DST_INTR_IDENT.

4.8.13.3 Port Module Interrupts

Each port module can generate an interrupt. Because there are too many modules to handle the

interrupts in parallel with the other source interrupts in the INTR_* registers, the port module interrupts

are aggregated in a separate source interrupt hierarchy before being presented to the interrupt controller

source logic as the DEV source interrupt.

Figure 132 •

Port Module Interrupt Logic

The module interrupt polarity is configurable in DEV_INTR_POL.DEV_INTR_POL[m].

DEV_INTR_RAW, DEV_INTR_TRIGGER, DEV_INTR_STICKY, DEV_INTR_BYPASS,

DEV_INTR_ENA, and DEV_INTR_IDENT works in the same way as the INTR_* counterparts.For more

information, see Interrupt Source Configuration, page 367.

The final step when handling module interrupts is an aggregation of all individual module interrupts to the

DEV source interrupt.

From source logic

Interrupt destination d

DST_INTR_MAP[d].DST_INTR_MAP

DST_INTR_IDENT[d].DST_INTR_IDENT

OR (n to 1)

AND

Filter Logic

00 Pass any.

01 Detect change.

10 Active to inactive.

11 Inactive to active.

Sticky

Hold interrupt

indication until

cleared by SW

AND

DEV_POL.DEV_POL[m]

Module interrupt m

DEV_INTR_TRIGGER.DEV_INTR_TRIGGER[m]

DEV_INTR_RAW.DEV_INTR_RAW[m]

DEV_INTR_STICKY.

DEV_INTR_STICKY[m]

DEV_INTR_BYPASS.DEV_INTR_BYPASS[m]

DEV_INTR_ENA.DEV_INTR_ENA[m]

DEV_INTR_IDENT.DEV_INTR_IDENT[m]

“DEV” Source Interrupt

OR (m to 1)

The last part OR’s all the m module

interrupts together to form the

aggregated “DEV” source interrupt.

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