 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
VSC7440 데이터시트(PDF) 395 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
VSC7440 데이터시트(HTML) 395 Page - Microsemi Corporation |
|
|
395 / 444 page  Electrical Specifications VMDS-10492 VSC7440 Datasheet Revision 4.2 378 The following illustration shows jitter transfer curves from REFCLK and REFCLK2 to all high-speed outputs. Figure 134 • REFCLK/REFCLK2 Jitter Transfer Curves REFCLK2 frequency REFCLK2_CONF = 010 ƒ –100 ppm 250 100 ppm MHz Clock duty cycle 40 60 % Measured at 50% threshold. Rise time and fall time, differential mode tR, tF 0.5 ns Within ±200 mV relative to VDD × 2/3. Jitter transfer from REFCLK to SERDES10G, bandwidth from 12 kHz to 1MHz 0.3 dB Jitter transfer from REFCLK to SERDES10G, bandwidth from 1 MHz to 7MHz 2dB Jitter transfer from REFCLK to SERDES10G, bandwidth above 7 MHz 2 – 20 × log (ƒ/7 MHz) dB REFCLK2 input RMS jitter, 12 kHz to 10 MHz 1psRMS Table 289 • REFCLK2 Reference Clock (continued) Parameter Symbol Minimum Typical Maximum Unit Condition 3 dB 0 dB –3 dB –6 dB –9 dB –12 dB –15 dB –18 dB –21 dB –24 dB 0.001 MHz 0.01 MHz 0.1 MHz Frequency (MHz) Gain vs. REFCLK/REFCLK2 Frequency 1 MHz 10 MHz 100 MHz 156.25 MHz 250 MHz 25 MHz 125 MHz |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
