VSC7440 datasheet(408/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

391

6.2.10

Serial Interface (SI) for Slave Mode

All serial interface (SI) slave mode timing requirements are specified relative to the input low and input

high threshold levels. The following illustrations show the timing parameters and measurement points for

SI input and output data.

Figure 138 •

SI Input Data Timing Diagram for Slave Mode

Figure 139 •

SI Output Data Timing Diagram for Slave Mode

Clock rise time and fall time

tR, tF

Between VIL(MAX) and

VIH(MIN). CL=30 pF.

SI_DO setup time to clock

tSU(DO)

SI_DO hold time from clock

tH(DO)

Enable active before first clock tLEAD

Enable inactive after clock

tLAG

SI_DI setup time to clock

tSU(DI)

SI_DI hold time from clock

tH(DI)

0ns

Frequency is programmable. The startup frequency is 4 MHz.

Table 310 •

SI Timing Specifications for Master Mode (continued)

Parameter

Symbol Minimum Maximum

Unit Condition

tW(CH)

tLAG1

tLEAD

tW(CL)

tSU(DI)

tH(DI)

SI_nCS0

(Input)

SI_CLK

(Input)

SI_DO

(Output)

High Impedance

SI_DI

(Input)

tLAG2

tW(EH)

Last data bit

tV(C)

tH(DO)

tDIS1

tDIS2

SI_nCS0

(Input)

SI_CLK

(Input)

SI_DO

(Output)

SI_DI

(Input)

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