VSC7511 datasheet(48/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

The sensitivity of the level detect circuit can be adapted to the input signal’s characteristics (amplitude

and noise). The threshold value for the level detect circuit is set in SERDES6G_IB_CFG.IB_VBCOM.

The default value is suitable for normal operation.

When the SerDes interface operates in 100BASE-FX mode, the input buffer of the SERDES6G macro

must also be configured for 100BASE-FX (SERDES6G_IB_CFG.IB_FX100_ENA).

During test or reception of low data rate signals (for example, 100BASE-FX), the DC-offset

compensation must be disabled. For all other modes, the DC-offset compensation must be enabled for

optimized performance. DC-offset compensation is controlled by

SERDES6G_IB_CFG1.IB_ENA_OFFSAC and SERDES6G_IB_CFG1.IB_ENA_OFFSDC.

3.4.7

SERDES6G Output Buffer Configuration

The SERDEDS6G output buffer supports the following configurable options.

•

Amplitude control

•

De-emphasis and output polarity inversion

•

Slew rate control

•

Skew adjustment

•

Idle mode

The maximum output amplitude of the output buffer depends on the output buffer’s supply voltage. For

interface standards requiring higher output amplitudes (backplane application or interface to optical

modules, for example), the output buffer can be supplied from a 1.2 V instead of a 1.0 V supply. By

default, the output buffer is configured for 1.2 V mode, because enabling the 1.0 V mode when supplied

from 1.2 V must be avoided. The supply mode is configured by

SERDES6G_OB_CFG.OB_ENA1V_MODE.

The output buffer supports a four-tap pre-emphasis realized by one pre-cursor, the center tap, and two

post cursors. The pre-cursor coefficient, C0, is configured by SERDES6G_SER_CFG.OB_PREC. C0 is a

5-bit value, with the most significant bit defining the polarity. The lower 4-bit value is hereby defined as

B0. The first post-cursor coefficient, C2, is configured by SERDES6G_OB_CFG.OB_POST0. C2 is a 6-

bit value, with the most significant bit defining the polarity. The lower 5-bit value is hereby defined as B2.

The second post-cursor coefficient, C3, is configured by SERDES6G_SER_CFG.OB_POST1. C3 is 5-bit

value, with the most significant bit defining the polarity. The lower 4-bit value is hereby defined as B3.

The center-tap coefficient, C1, is a 6-bit value. Its polarity can be programmed by

SERDES6G_OB_CFG.OB_POL, which is hereby defined as p1. For normal operation

SERDES6G_OB_CFG.OB_POL must be set to 1. The value of the 6 bits forming C1 is calculated by the

following equation.

Equation 1: C1: (64 – (B0 + B2 + B3)) × p1

The output amplitude is programmed by SERDES6G_OB_CFG1.OB_LEV, which is a 6-bit value. This

value is internally increased by 64 and defines the amplitude coefficient K. The range of K is therefore 64

to 127. The differential peak-peak output amplitude is given by 8.75 mV × K. The maximum peak-peak

output amplitude depends on the data stream and can be calculated to:

Equation 2: H(Z) = 4.375 mVpp × K × (C0 × z1 + C1 × z0 + C2 × z–1 + C3 × z–2)/64

with zn denoting the current bits of the data pattern defining the amplitude of Z. The output amplitude also

depends on the output buffer’s supply voltage.

The configuration bits are summarized in the following table.

Table 20 •

De-Emphasis and Amplitude Configuration

Configuration

Value

Description

OB_PREC

Signed 5-bit value

Pre-cursor setting C0. Range is –15 to 15.

OB_POST0

Signed 6-bit value

First post-cursor setting C2. Range is –31 to 31.

OB_POST1

Signed 5-bit value

Second post-cursor setting C3. Range is –15 to 15.

OB_LEV

Unsigned 6-bit value

Amplitude coefficient, K = OB_LEV + 64. Range is 0 to 63.

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