SAMV71Q21 datasheet(30/41 Pages) MICROCHIP

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17.

Serial Synchronous Controller (SSC)

17.1

Inverted Left/Right Channels

When the SSC is in Slave mode, the TF signal is derived from the codec and not controlled by the SSC.

The SSC transmits the data when detecting the falling edge on the TF signal after the SSC transmission

is enabled. In some cases of overflow, a left/right channel inversion may occur. When this occurs, the

SSC must be reinitialized.

Workaround

Using the SSC in Master mode will ensure that TF is controlled by the SSC and no error occurs. If the

SSC must be used in TF Slave mode, the SSC must be started by writing TXEN and RXEN

synchronously with the TXSYN flag rising in the SSC_SR.

Affected Silicon Revisions

17.2

Unexpected TD Output Delay

An unexpected delay on TD output may occur when the SSC is configured with the following conditions:

•

The START bit in the RCMR register = Start on falling edge/Start on Rising edge/Start on any edge

•

The FSOS bit in the RFMR register = None (input)

•

The START bit in the TCMR register = Receive Start

Under these conditions, an unexpected delay of two or three system clock cycles is added to the TD

output.

Workaround

None.

Affected Silicon Revisions

SAM E70/S70/V70/V71 Family

Serial Synchronous Controller (SSC)

Datasheet Errata

DS80000767C-page 30

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