6.

Extended DMA Controller (XDMAC)

6.1

TCM Accesses

If TCM accesses are generated through the AHBS port of the core, only 32-bit accesses are supported.

Accesses that are not 32-bit aligned may overwrite bytes at the beginning and at the end of 32-bit words.

Workaround

The user application must use 32-bit aligned buffers and buffers with a size of a multiple of 4 bytes when

transferring data to or from the TCM through the AHBS port of the core.

Affected Silicon Revisions

A

B

X

X

6.2

Byte and Half-Word Accesses

If XDMAC is used to transfer 8-bit or 16-bit data in Fixed Source Address mode or Fixed Destination

Address mode, source and destination addresses are incremented by 8-bit or 16-bit.

Workaround

The user can resolve this issue by setting the source and destination addressing mode to use microblock

and data striding with microblock stride set to 0 and data stride set to -1.

Affected Silicon Revisions

A

B

X

X

6.3

Request Overflow Error

When a DMA memory-to-memory transfer is performed, if the hardware request line selected by the field

PERID bit in the XDMAC_CCx register toggles when the copy is enabled, the ROIS bit in the

XDMAC_CISx register is set incorrectly. The memory transfer proceeds normally and the data area is

correctly transferred.

Workaround

Configure the PERID bit to an unused peripheral ID.

Affected Silicon Revisions

A

B

X

X

SAM E70/S70/V70/V71 Family

Extended DMA Controller (XDMAC)

Datasheet Errata

DS80000767C-page 16