CS98200 datasheet(35/60 Pages) CIRRUS

35 / 60 page

DS581PP2

CS98200

Next Generation DVD Processor

6. MEMORY MAP

6.1

Processor Memory Map

The CS98200 externally supports up to 32 Mbytes DRAM and 16 Mbytes ROM/NVRAM. Table 9,

Table 10, and Table 11 on the next page list the memory map as viewed by the RISC processors, and

identifies whether each segment is mapped or cacheable.

For detailed information on programming CS98200 memory, see

CS98200 Memory Interface User’s

Manual (DS525UMD1).

Address

Description

Cached

0x8000_0000 - 0x8000_7FFF

Internal SRAM (32 Kbytes)

Yes

0x8200_0000 - 0x83FF_FFFF

External DRAM (32 Mbytes)

Yes

0x9400_0000 - 0x97FF_FFFF

External DRAM w/ Dcache flush (32 Mbytes)

Yes

0x9800_0000 - 0x9BFF_FFFF

External ROM/NVRAM read/write (16 Mbytes)

Yes

0x9C00_0000 - 0x9FFF_FFFF

External ROM/NVRAM read only (16 Mbytes)

Yes

0xA000_0000 - 0xA000_7FFF

Internal SRAM (32 Kbytes)

0xA200_0000 - 0xA3FF_FFFF

External DRAM (32 Mbytes)

0xB000_0000 - 0xB003_FFFF

Internal registers and SRAMs

0xB400_0000 - 0xB7FF_FFFF

External DRAM w/ Dcache flush (32 Mbytes)

0xB800_0000 - 0xBBFF_FFFF

External ROM/NVRAM read/write (16 Mbytes)

0xBC00_0000 - 0xBFFF_FFFF

External ROM/NVRAM read only (16 Mbytes)

Table 9. Memory Map-RISC0 Processor

Host Byte Address

Description

0x0000_0000 - 0x0003_FFFF

Internal registers and SRAMs

0x1000_0000 - 0x11FF_FFFF

External DRAM (32 Mbytes)

0x1200_0000 - 0x13FF_FFF

Internal SRAM

0x1400_0000 - 0x14FF_FFFF

External ROM/NVRAM space (16 Mbytes)

Table 10. Host Debug Port Address Map

Byte Address Offset

Description

0x0000_0000 - 0x0003_FFFF (I/O space)

Internal Registers and SRAMs

0x0000_0000 - 0x01FF_FFFF (memory space)

External DRAM (32 Mbytes)

0x0200_0000 - 0x0200_7FFF (memory space)

Internal SRAM (32 Kbytes)

Table 11. DSP Address Map

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