WM8742GEDSSLASHV datasheet(32/66 Pages) CIRRUS

32 / 66 page

WM8742

Rev 4.4

ADDRESS

BITS

LABEL

DEFAULT

DESCRIPTION

DACLLSB

Attenuation

00h

[4:0]

LAT[4:0]

00 (0dB)

LSBs of attenuation data for left channel in 0.125dB steps. See

Table 25 for details.

UPDATE

Attenuation data load control for left channel.

0 =

Store LAT[4:0] value but don’t update

1 = Store LAT[4:0] and update attenuation on registers 0-3

DACLMSB

Attenuation

01h

[4:0]

LAT[9:5]

00 (0dB)

MSBs of attenuation data for left channel in 4dB steps. See Table

25 for details.

UPDATE

Attenuation data load control for left channel.

0 =

Store LAT[9:5] value but don’t update

1 = Store LAT[9:5] and update attenuation on registers 0-3

DACRLSB

Attenuation

02h

[4:0]

RAT[4:0]

00 (0dB)

LSBs of attenuation data for right channel in 0.125dB steps. See

Table 25 for details.

UPDATE

Attenuation data load control for right channel.

0 =

Store RAT[4:0] value but don’t update

1 = Store RAT[4:0] and update attenuation on registers 0-3

DACRMSB

Attenuation

03h

[4:0]

RAT[9:5]

00 (0dB)

MSBs of attenuation data for right channel in 4dB step. See Table

25 for details.

UPDATE

Attenuation data load control for right channel.

0 =

Store RAT[9:5] value but don’t update

1 = Store RAT[9:5] and update attenuation on registers 0-3

Table 24 Attenuation Control

Note:

The UPDATE bit is not latched. If UPDATE=0, the attenuation value will be written to the pre-latch but not applied to the

relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input

sample.

DAC OUTPUT ATTENUATION

Registers LAT[9:0] and RAT[9:0] control the left and right channel attenuation. Table 25 shows how

the attenuation levels are configured by the 10-bit words.

L/RAT[9:0]

ATTENUATION LEVEL

000(hex)

0dB

001(hex)

-0.125dB

3FE(hex)

-127.75dB

3FF(hex)

dB (mute)

Table 25 Attenuation Control Levels

ATTENUATION CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and

right channel DACs from the next audio input sample.

No update to the attenuation registers is

required for ATC to take effect.

Right channels register settings are preserved regardless of the

status of ATC.

WM8742GEDS/V 데이터시트(PDF) 32 Page - Cirrus Logic

WM8742GEDS/V 데이터시트(HTML) 32 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

데이터시트 다운로드

링크 URL