MCP2517FD datasheet(49/98 Pages) MICROCHIP

49 / 98 page

 2017-2018 Microchip Technology Inc.

DS20005688B-page 49

MCP2517FD

bit 15-11

Unimplemented:

Read as ‘0’

bit 10

FRESET

: FIFO Reset bit( 3)

= FIFO will be reset when bit is set; cleared by hardware when FIFO was reset. User should wait

until this bit is clear before taking any action.

= No effect

bit 9

TXREQ

: Message Send Request bit( 2)

= Requests sending a message; the bit will automatically clear when all the messages queued in

the TXQ are successfully sent.

= Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

bit 8

UINC

: Increment Head bit

When this bit is set, the FIFO head will increment by a single message.

bit 7

TXEN

: TX Enable

= Transmit Message Queue. This bit always reads as ‘1’.

bit 6-5

Unimplemented:

Read as ‘0’

bit 4

TXATIE

: Transmit Attempts Exhausted Interrupt Enable bit

= Enable interrupt

= Disable interrupt

bit 3

Unimplemented:

Read as ‘0’

bit 2

TXQEIE

: Transmit Queue Empty Interrupt Enable bit

= Interrupt enabled for TXQ empty

= Interrupt disabled for TXQ empty

bit 1

Unimplemented:

Read as ‘0’

bit 0

TXQNIE

: Transmit Queue Not Full Interrupt Enable bit

= Interrupt enabled for TXQ not full

= Interrupt disabled for TXQ not full

CiTXQCON – TRANSMIT QUEUE CONTROL REGISTER (CONTINUED)

Note 1:

These bits can only be modified in Configuration mode.

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

FRESET is set while in Configuration mode and is automatically cleared in Normal mode.

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