MCP2517FD datasheet(53/98 Pages) MICROCHIP

53 / 98 page

 2017-2018 Microchip Technology Inc.

DS20005688B-page 53

MCP2517FD

bit 15-11

Unimplemented:

Read as ‘0’

bit 10

FRESET:

FIFO Reset bit( 3)

= FIFO will be reset when bit is set; cleared by hardware when FIFO was reset. User should wait

until this bit is clear before taking any action.

= No effect

bit 9

TXREQ:

Message Send Request bit( 2)

TXEN = 1 (FIFO configured as a Transmit FIFO)

= Requests sending a message; the bit will automatically clear when all the messages queued in

the FIFO are successfully sent.

= Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

TXEN = 0 (FIFO configured as a Receive FIFO)

This bit has no effect.

bit 8

UINC:

Increment Head/Tail bit

TXEN = 1 (FIFO configured as a Transmit FIFO)

When this bit is set, the FIFO head will increment by a single message.

TXEN = 0 (FIFO configured as a Receive FIFO)

When this bit is set, the FIFO tail will increment by a single message.

bit 7

TXEN:

TX/RX FIFO Selection bit( 1)

= Transmit FIFO

= Receive FIFO

bit 6

RTREN

: Auto RTR Enable bit

= When a remote transmit is received, TXREQ will be set.

= When a remote transmit is received, TXREQ will be unaffected.

bit 5

RXTSEN

: Received Message Time Stamp Enable bit( 1)

1 = Capture time stamp in received message object in RAM.

0 = Don’t capture time stamp.

bit 4

TXATIE

: Transmit Attempts Exhausted Interrupt Enable bit

= Enable interrupt

= Disable interrupt

bit 3

RXOVIE

: Overflow Interrupt Enable bit

= Interrupt enabled for overflow event

= Interrupt disabled for overflow event

bit 2

TFERFFIE

: Transmit/Receive FIFO Empty/Full Interrupt Enable bit

TXEN = 1 (FIFO configured as a Transmit FIFO)

Transmit FIFO Empty Interrupt Enable

= Interrupt enabled for FIFO empty

= Interrupt disabled for FIFO empty

TXEN = 0 (FIFO configured as a Receive FIFO)

Receive FIFO Full Interrupt Enable

= Interrupt enabled for FIFO full

= Interrupt disabled for FIFO full

bit 1

TFHRFHIE

: Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit

TXEN = 1 (FIFO configured as a Transmit FIFO)

Transmit FIFO Half Empty Interrupt Enable

= Interrupt enabled for FIFO half empty

= Interrupt disabled for FIFO half empty

TXEN = 0 (FIFO configured as a Receive FIFO)

Receive FIFO Half Full Interrupt Enable

= Interrupt enabled for FIFO half full

= Interrupt disabled for FIFO half full

CiFIFOCONm – FIFO CONTROL REGISTER m, (m = 1 TO 31) (CONTINUED)

Note 1:

These bits can only be modified in Configuration mode.

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

FRESET is set while in Configuration mode and is automatically cleared in Normal mode.

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