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NTP53X2 데이터시트(PDF) 48 Page - NXP Semiconductors |
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NTP53X2 데이터시트(HTML) 48 Page - NXP Semiconductors |
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48 / 133 page ![]() NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 48 / 133 Bit Name Value Description 1b Section 3 is not readable by I2C 0b Section 2 is readable by I2C 2 Section 2 1b Section 2 is not readable by I2C 0b Section 1 is readable by I2C 1 Section 1 1b Section 1 is not readable by I2C 0b Section 0 is readable by I2C 0 Section 0 1b Section 0 is not readable by I2C Note: Section 7 (default SRAM content) and Section 8 (Device configuration lock bytes) are always readable. In case of not readable and/or not writeable, IC responds with an NACK from I2C perspective and with an error from NFC perspective, when trying to access locked sections. 8.1.4 Session registers After POR, the content of the configuration settings (see Section 8.1.3) is loaded into the session register. The values of session registers can be changed during a session. Change to session registers take effect immediately, but only for the current communication session. After POR, the session registers values will again contain the configuration register values as before. To change the default behavior, changes to the related configuration bytes are needed, but the related effect will only be visible after the next POR. Session registers starting from block A3h until the end may be write protected with LOCK_REGISTER bit. Reading and writing the session registers via I2C can only be done with READ REGISTER and WRITE REGISTER commands. Most of the parameters are defined in the configuration memory section. Table 85. Session Register Location Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 Remark A0h 10A0h STATUS_REG RFU Status Register (see Section 8.1.4.1) A1h 10A1h CONFIG_REG Configuration (see Section 8.1.4.2) A2h 10A2h SYNC_DATA_BLOCK_REG RFU Block Address (see Section 8.1.4.3) A3h 10A3h PWM_GPIO_CONFIG_REG RFU PWM and GPIO Configuration(see Section 8.1.4.4) |
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