NTP53X2 datasheet(53/133 Pages) NXP

53 / 133 page

NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

53 / 133

8.1.4.3 Synchronization block register

The terminator block maybe changed during one session from both interfaces (see

Section 8.1.3.14). Both interfaces do have read and write access.

8.1.4.4 Pulse Width Modulation and GPIO configuration register

These session register bytes define the various configurations for GPIO/PWM use case

(see Section 8.1.3.13). From NFC perspective IN_STATUS bits are read only, all others

maybe changed during a session. From I2C perspective, all bits are read only. For details

refer to Section 8.3.3 and Section 8.3.4.

Table 93. PWM and GPIO Configuration Register Location (PWM_GPIO_CONFIG_REG)

Block Address

NFC

I2C

Byte 0

Byte 1

Byte 2

Byte 3

A3h

10A3h

PWM_GPIO_

CONFIG_0_REG

PWM_CONFIG_

1_REG

RFU

Table 94. PWM and GPIO Configuration Register Definition (PWM_GPIO_CONFIG_0_REG)

Bit

Name

Access

Value

Description

NFC acc. I2C acc.

Output status on pad is LOW

SDA_GPIO1_OUT_STATUS

R/W

Output status on pad is HIGH

Output status on pad is LOW

SCL_GPIO0_OUT_STATUS

R/W

Output status on pad is HIGH

SDA_GPIO1_SDA_IN_STATUS

Input status

SCL_GPIO0_IN_STATUS

Input status

Output

SDA_GPIO1

R/W

Input

Output

SCL_GPIO0

R/W

Input

GPIO

SDA_GPIO1_PWM1

R/W

PWM

GPIO

SCL_GPIO0_PWM0

R/W

PWM

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