NTP53X2 datasheet(104/133 Pages) NXP

104 / 133 page

NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

104 / 133

The configurable events indicated at event detection pin are:

• The presence/absence of the NFC field

• Data read/written in pass-through mode

• Arbiter locked/unlocked EEPROM to NFC interface

• NDEF Message TLV length field is ZERO/non-ZERO

• IC is/is not in standby mode

• Dedicated config bit is ZERO

• Write/Read command ongoing

Event detection pin is an active LOW signal. Due to open-drain implementation an

external pull-up resistor shall be used on this pin.

How to use the event detection pin in applications is described in AN11203.

8.3.3 GPIO

I2C pins (SCL/SDA) are multiplexed and can be used as general-purpose input/

output pins linked to configuration/session bits. When configured as GPIO pins, I2C

communication is not possible anymore.

At POR, the GPIO are set to high-impedance state. When configuration is read, the pins

are controlled to behave as per the configuration.

GPIOs can be configured to be either input or output (see Section 8.1.3.15). In input

mode, the status of the pad will be available in one of the session register bits. In output

mode status depends on the session register/config bits content.

How to use the GPIO pins in applications is described in AN11203.

8.3.4 PWM

I2C pins (SDA/SCL) and ED pin are multiplexed and can be used as a pulse width

modulation output. I2C pins have push-pull architecture, ED pin is an open-drain

implementation, which means the PWM signal gets inverted.

PWM resolution, pre-scalar factor (see Section 8.1.3.15) as well as duty cycle can be

configured using configuration bytes (see Section 8.1.3.16).

The pulse width modulation resolution (PWMx_RESOLUTION_CONF) defines the

maximum number of pulses that are available in the given PWM period. PWM resolution

can be set independently for both outputs to either 6, 8, 10 or 12 bits.

The 2-bit PWMx_PRESCALE value divides the PWM input frequency (1695 kHz) by a

factor of 1, 2, 4 or 8.

Table 230. Pulse Width Modulation Frequency

Pre-scalar

Resolution

00b

01b

10b

11b

12 bit

413 Hz

206 Hz

103 Hz

52 Hz

10 bit

1.7 kHz

825.0 Hz

412.6 Hz

206.2 Hz

8 bit

6.6 kHz

3.3 kHz

1.7 kHz

825.0 Hz

6 bit

26.4 kHz

13.2 kHz

6.6 kHz

3.3 kHz

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