ADC32RF83 datasheet(45/138 Pages) TI

45 / 138 page

ADC A

ADC B

NCO

To JESD ChA

NCO

To JESD ChB

ADC32RF80, ADC32RF83

www.ti.com

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

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8.3.4.3.12

Latency with Decimation Options

Device latency in 12-bit bypass mode (with LMFS = 8224) is 424 clock cycles. When the DDC option is used,

latency increases as a result of decimation filters, as described in Table 5.

Table 5. Latency with different Decimation options

DECIMATION OPTION

TOTAL LATENCY, DEVICE CLOCK CYCLES

Divide-by-4

516

Divide-by-6

746

Divide-by-8

621

Divide-by-9

763.5

Divide-by-10

811

Divide-by-12

897

Divide-by-16

1045

Divide-by-18

1164

Divide-by-20

1256

Divide-by-24

1443

Divide-by-32

1773

8.3.4.4 Digital Multiplexer (MUX)

The ADC32RF8x supports a mode where the output data of the ADC channel A can be routed internally to the

digital blocks of both channel A and channel B. The ADC channel B can be powered down as shown in

Figure 120. In this manner, the ADC32RF8x can be configured as a single-channel ADC with up to four

independent DDC chains or two wideband DDC chains. All decimation filters and JESD204B format

configurations are identical to the two ADC channel operation.

Figure 120. Digital Multiplexer Option

8.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers

The ADC32RF8x is equipped with three independent, complex NCOs per ADC channel. The oscillator generates

a complex exponential sequence, as shown in Equation 2.

x[n] = e

–jωn

where

•

frequency (ω) is specified as a signed number by the 16-bit register setting

(2)

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