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ADC32RF83 데이터시트(PDF) 62 Page - Texas Instruments

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부품명 ADC32RF83
상세설명  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF83 데이터시트(HTML) 62 Page - Texas Instruments

Back Button ADC32RF83 Datasheet HTML 58Page - Texas Instruments ADC32RF83 Datasheet HTML 59Page - Texas Instruments ADC32RF83 Datasheet HTML 60Page - Texas Instruments ADC32RF83 Datasheet HTML 61Page - Texas Instruments ADC32RF83 Datasheet HTML 62Page - Texas Instruments ADC32RF83 Datasheet HTML 63Page - Texas Instruments ADC32RF83 Datasheet HTML 64Page - Texas Instruments ADC32RF83 Datasheet HTML 65Page - Texas Instruments ADC32RF83 Datasheet HTML 66Page - Texas Instruments Next Button
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background image
tSLOADS
R/W
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDIN
SCLK
SEN
RESET
A11 A10
A9
A8
A7
A6
M
P
CH
Register Address [11:0]
Register Data [7:0]
tDH
tDSU
tSLOADH
tSCLK
62
ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.4.3 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the
device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active
(low), as shown in Figure 135. The interface can function with SCLK frequencies from 20 MHz down to low
speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 25.
The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits
to distinguish between read/write, page and register, and individual channel access, as described in Table 26.
Figure 135. SPI Timing Diagram
Table 25. SPI Timing Information
MIN
TYP
MAX
UNIT
fSCLK
SCLK frequency (equal to 1 / tSCLK)
1
20
MHz
tSLOADS
SEN to SCLK setup time
50
ns
tSLOADH
SCLK to SEN hold time
50
ns
tDSU
SDIN setup time
10
ns
tDH
SDIN hold time
10
ns
tSDOUT
Delay between SCLK falling edge to SDOUT
10
ns



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