ADC32RF83 datasheet(125/138 Pages) TI

125 / 138 page

Temperature (°C)

-40

-15

-100

-90

-80

-70

-60

-50

-40

Average of fS/8

Average of 3fS/8

Average of fS/4

Temperature (°C)

-40

-15

-100

-90

-80

-70

-60

-50

-40

-30

-20

Average of fS/4

Average of fS/8

Average of 3fS/8

125

ADC32RF80, ADC32RF83

www.ti.com

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

Submit Documentation Feedback

9.1.5.1 Bypassing the Offset Corrector Block

When the offset corrector is bypassed, offset mismatch among interleaving ADC cores appears in the ADC

output spectrum. To correct the effects of mismatch, place the ADC in an idle channel state (no signal at the

ADC inputs) and the corrector must be allowed to run for some time to estimate the mismatch, then the corrector

is frozen so that the last estimated value is held. Required register writes are provided in Table 120.

Table 120. Freezing and Bypassing the Offset Corrector Block

STEP

COMMENT

STEPS FOR FREEZING THE CORRECTOR BLOCK

—

Signal source is turned off. The device detects an idle channel at its input.

—

Wait for at least 0.4 ms for the corrector to estimate the internal offset

Address 4001h, value 00h

Select Offset Corr Page Channel A

Address 4002h, value 00h

Address 4003h, value 00h

Address 4004h, value 61h

Address 6068h, value C2h

Freeze the corrector for channel A

Address 4003h, value 01h

Select Offset Corr Page Channel B

Address 6068h, value C2h

Freeze the corrector for channel B

—

Signal source can now be turned on

STEPS FOR BYPASSING THE CORRECTOR BLOCK

Address 4001h, value 00h

—

Address 4002h, value 00h

Address 4003h, value 00h

Address 4004h, value 61h

Select Offset Corr Page Channel A

Address 6068h, value 46h

Disable the corrector for channel A

Address 4003h, value 01h

Select Offset Corr Page Channel B

Address 6068h, value 46h

Disable the corrector for channel B

9.1.5.1.1

Effect of Temperature

Figure 259 and Figure 260 show the behavior of nfS / 8 tones with respect to temperature when the offset

corrector block is frozen or disabled.

Figure 259. Offset Corrector Block Frozen at Room

Temperature

Figure 260. Offset Corrector Block Disabled

ADC32RF83 데이터시트(PDF) 125 Page - Texas Instruments

ADC32RF83 데이터시트(HTML) 125 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL