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MTC20454

Receive / Transmit Interface

The digital interface is based on a 4 * 8.832 MHz (35.328 MHz) clock. The 8.832MHz 12 bits A/D output

signal or the D/A input signal are SIPO multiplexed over 4 parallel 35.328MHz data lines in the following

table. If OSR = 2 bit is selected, CLKNIB is used as nibble clock (17.664 MHz, disabled in normal mode),

and all the

Table 2. RXi, TXi, CLKWD periods are twice

TX / TXE Signal Dynamic Range

The dynamic range of the signal for both DACs is 12 bits extracted from the available signed 16 bit repre-

sentation coming from the digital processor.

The maximal positive number is 2 11 -1, the most negative number is -2 11, the 3 least significant bits are

ignored.

Any signal exceeding these limits is clamped to the maximal value.

Table 3. TX bit map

RX Signal Dynamic Range

The dynamic range of the signal from the ADC is limited to 13 bits. hose bits are converted to a signed

representation with a maximal positive number of 2 12 -1 and a most negative number of -2 12.

The 2 LSBs are filled with ‘0’.

Table 4. RX bit map in normal mode

Packet Number

Bus Line

Word bit

Packet 1

RX0/TX0

Bit 0

RX1/TX1

Bit 1

RX2/TX2

Bit 2

RX3/TX3

Bit 3

Packet 2

RX0/TX0

Bit 4

RX1/TX1

Bit 5

RX2/TX2

Bit 6

RX3/TX3

Bit 7

Packet 3

RX0/TX0

Bit 8

RX1/TX1

Bit 9

RX2/TX2

Bit 10

RX3/TX3

Bit 11

Packet 4

RX0/TX0

Bit 12

RX1/TX1

Bit 13

RX2/TX2

Bit 14

RX3/TX3

Bit 15

Sign

Sign

B10

B9B8B7B6B5

B4

B3

B2

B1

B0

n.u

n.u

n.u

Sign

B12

B11

B10

B9

B8

B7

B6

B5B4B3B2B1B0

0

0