MTC20454

12/15

Receive / Transmit Interface Timing

This interface is a triple (RX,TX, TXE) nibble-serial interface running at 8.8 MHz sampling (normal mode).

The data are represented in 16 bits format, and transferred in groups of 4 bits (nibbles). The LSBs are

transferred first. The MTC20454 generates a nibble clock (= master clock in normal mode, CLKNIB in

OSR = 2 mode) and word signals shared by the three interfaces.

Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going

edge of CLKM/CLKNIB. This holds for the data stream from MTC20454 and rom the digital processor. Da-

ta,

CLWD set-up and hold times are 5 ns with reference to the falling edge of CLKM/CLKNIB. RXD is sampled

with CLKM rising edge.

Figure 8. TX/RX Digital Interface Timing

Table 5. TX/RX Digital Interface timing

Reset Function

The MTC20454 is placed in reset mode when the RESETN pin is pulled to ground (active low signal). The

chip status is depicted in the following table:

Symbol

Parameter

Min

Typ

Max

Ts

Setup time

0.5 ns

-

-

Th

Hold time

0.2 ns

-

-

Tdv

Data valid

0.5 ns

-

4 ns

Reset

CLKM pin is replicating the CLKIN input clock. System clock available

CLKWD is not generated. The pin stays at high level

Digital blocks are in reset: no activity

Analog blocks are in powerdown

External driver is forced to powerdown

TXDx

N0

Tdv

N1

N2

N3

RXDx

CLKM

35.328Mhz

CLKWD

8.832Mhz

Th

Tdv

Ts